The major disadvantage of a standard bus topology is the constraint of being able to realize only one communication at a time (the tasks may take place in parallel but the communications are only done in a sequential). As these communications are handled by the bus arbiter, a Bottleneck when the number of communications increases, but also when the bandwidth constraints of several communications become important.This arbitration plays a predominant role because it authorizes communications on the bus but it is also in charge of resolving the conflicts (several requests of communications at the same time). This arbitration implies therefore a limitation on the number of IP connected to the bus to a dozen elements.
This work elaborates the AMBA bus interface with four masters interacting with single memory system, using Arbiter between memory controller and other supporting peripherals. Different module of i.e., AHB MSTER, AHB SLAVE INTERFACE AND AHB ARBITER(round robin algorithm)has been developed with VHDL. Further integration with FIFO, RAM and ROM with memory controller is done. The Four AHB master initiates the operations and generates the necessary control signals on single bus to memory controller with the help of arbiter. The proposed architecture shows the area efficient management as compared to previous researches of multiple data communication in AHB BUS system. The system model is synthesized with Xilinx XC6vx75t-2ff484 and simulated with MODELSIM.

This paper elaborates the AMBA bus interface bridge between memory controller and other supporting peripheral. The work claims the integration with FIFO, RAM and ROM with slave interface and the master of AHB bus. The AHB master initiates the operation and generates the necessary control signal. Memory controller is implemented with finite state machine considering with all the peripheral works in synchronous mode. Despite these shortcomings of the work performed study and development that followed has led the development of a memory controller on AMBA-AHB bus at a very advanced stage and next to prototyping. VHDL code is utilized to develop the design and it is synthesized in Xilinx Virtex 6 device (XC6VCX75T). The design claims a minor area overhead with improvement in speed 185.134 MHz.