In the Current scenario of higher level of integration the most encountered problems are heat dissipation and information loss on each and every computation. For the sake of eliminating these issues Reversible computing is being adopted as a preferable substitute of digital circuit design. This paper focuses on the design of Reversible Ring Counter and Twisted Ring Counter using Reversible D flip flop implemented with the Novel Design of Feynman and Fredkin Gate. Ring counters are commonly found in applications used to count the data in a continuous loop as well as in frequency divider circuits. While twisted (or Johnson) ring counter is used as three-phase square wave generators (using 3 flip-flops) and quadrature oscillator circuits (using 2 flip-flops) etc. The response of the proposed counter circuit is tested with the help of QCADesigner 2.0.3 simulation tool and the Energy dissipation is analyzed by the use of QCA Designer-E tool.

In the present era of miniaturization, higher power dissipation in form of heat has become a very critical issue for the digital Circuits. This excessive heat may result in the lower chip reliability and even destroy it. Due to this reason a substitute is required for the traditional CMOS technology, Reversible logic is a paradigm in this direction. This paper encompasses of the newly proposed SA reversible logic and basic combinational implementations using a single SA building block only resulting in lower circuit level complexity as well as hardware requirement. The output responses and energy dissipation of proposed SA reversible logic are verified and calculated with the help of QCADesigner and QCADesigner-E simulation tools respectively.