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International Journal of Modern Education and Computer Science (IJMECS)

ISSN: 2075-0161 (Print), ISSN: 2075-017X (Online)

Published By: MECS Press

IJMECS Vol.11, No.10, Oct. 2019

An Optimized Approach towards Reversible Adder/Subtractor Design on QCA

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Author(s)

Snigdha Singh, Abhinay Choudhary, Manoj Kumar Jain

Index Terms

Quantum cost, garbage output, constant input, reversible logic, low power CMOS Technology.

Abstract

In the present era of miniaturization, higher power dissipation in form of heat has become a very critical issue for the digital Circuits. This excessive heat may result in the lower chip reliability and even destroy it. Due to this reason a substitute is required for the traditional CMOS technology, Reversible logic is a paradigm in this direction. This paper encompasses of the newly proposed SA reversible logic and basic combinational implementations using a single SA building block only resulting in lower circuit level complexity as well as hardware requirement. The output responses and energy dissipation of proposed SA reversible logic are verified and calculated with the help of QCADesigner and QCADesigner-E simulation tools respectively.

Cite This Paper

Snigdha Singh, Abhinay Choudhary, Manoj Kumar Jain, " An Optimized Approach towards Reversible Adder/Subtractor Design on QCA", International Journal of Modern Education and Computer Science(IJMECS), Vol.11, No.10, pp. 47-53, 2019.DOI: 10.5815/ijmecs.2019.10.06

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