This paper reviews the design of phase locked loop (PLL) using recently reported charge pump circuits. Lock time, phase noise, lock range and reference spur of each charge pump circuit are investigated. Though improved charge pump circuits are designed recently, their performance is not as effective as the basic charge pump PLL (CP-PLL). Initially the design of PLL using the basic charge pump is completed in this paper and then the PLL using improved charge pumps are redesigned in CMOS 180 nm technology and simulated using Cadence Virtuoso Analog Design Environment. Finally all the charge pumps are compared with respect to the PLL performances. The current starved voltage controlled oscillator (VCO) used for the design of PLL brings about a tuning range of 119.5 MHz to 2.3 GHz. The PLL using different charge pumps produces a lock time which varies from 204 ns to 329 ns. The other parameters like lock range, phase noise and reference spur are also examined.