This paper presents one novel algorithm for minimization of non-zero coefficients of Finite Impulse response (FIR) pulse-shaping filter, mostly employed in practical digital communication system to alleviate the difficulties resulting from Inter Symbol Interference (ISI), followed by its hardware optimization on a Field Programmable Gate Array (FPGA) chip . Filter performance has been demonstrated through the inclusion of impulse response, magnitude spectrum and requirement of various hardware blocks. The supremacy of our algorithm has been substantiated by comparing its performance with other existing models of different length. From the simulation results, it has been concluded that the proposed FIR filter provides a considerable reduction in the number of non-zero coefficients without affecting its performance significantly.

Reduction of computational complexity of digital hardware has drawn the special attention of researchers in recent past. Proper emphasis is needed in this regard towards the settlement of computationally efficient as well as functionally competent design of digital systems. In this communication, we have made one novel attempt for designing multiplier-free Finite duration Impulse Response (FIR) digital filter using one robust evolutionary optimization technique, called Differential Evolution (DE). The search has been directed through two sequentially opposite paths which include quantization and optimization as fundamental operations. Besides performing a detailed comparative analysis between these two proposed approaches; the performance evaluation of the designed filter with other existing discrete coefficient FIR models has also been carried out. Finally, the optimum search method for realizing the required set of specifications has been suggested.