International Journal of Image, Graphics and Signal Processing (IJIGSP)
IJIGSP Vol. 4, No. 4, 8 May 2012
Cover page and Table of Contents: PDF (size: 2059KB)
Design and Implementation of a Power Efficient Pulse-shaping Finite Impulse Response Filter on a Field Programmable Gate Array Chip
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Author(s)
Puja Kumari
1,*
Rajeev Gupta
1
Abhijit Chandra
1
Index Terms
Finite Impulse Response (FIR) filter, Power efficiency, Pulse-shaping filter, Raised Cosine (RC) filter
Abstract
This paper presents one novel algorithm for minimization of non-zero coefficients of Finite Impulse response (FIR) pulse-shaping filter, mostly employed in practical digital communication system to alleviate the difficulties resulting from Inter Symbol Interference (ISI), followed by its hardware optimization on a Field Programmable Gate Array (FPGA) chip . Filter performance has been demonstrated through the inclusion of impulse response, magnitude spectrum and requirement of various hardware blocks. The supremacy of our algorithm has been substantiated by comparing its performance with other existing models of different length. From the simulation results, it has been concluded that the proposed FIR filter provides a considerable reduction in the number of non-zero coefficients without affecting its performance significantly.
Cite This Paper
Puja Kumari,Rajeev Gupta,Abhijit Chandra,"Design and Implementation of a Power Efficient Pulse-shaping Finite Impulse Response Filter on a Field Programmable Gate Array Chip", IJIGSP, vol.4, no.4, pp.1-10, 2012. DOI: 10.5815/ijigsp.2012.04.01
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