Work place: ITM University/Department of EECE, Gurgaon, 122001, India
E-mail: priyankaojha96@gmail.com
Website:
Research Interests: Computational Engineering, Engineering
Biography
Priyanka Ojha was born in Hisar, Haryana, India on September 2, 1989. She received the B.Tech degree from Kurukshetra University in 2013. She is currently involved in M.Tech work in ITM University. Her area of research is Low Power Design Techniques.
DOI: https://doi.org/10.5815/ijisa.2015.08.06, Pub. Date: 8 Jul. 2015
Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit.
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