In this paper, pipelined Vedic-Array multiplier architecture is proposed. The most significant aspect of the proposed multiplier architecture method is that, the developed multiplier architecture is designed based on the Vedic and Array methods of multiplier architecture. The multiplier architecture is optimized in terms of multiplication and addition to achieve efficiency in terms of area, delay and power. This also gives chances for modular design where smaller block can be used to design the bigger one. So the design complexity gets reduced for inputs of larger number of bits and modularity gets increased. The proposed Vedic-Array multiplier is coded in Verilog, synthesized and simulated using EDA (Electronic Design Automation) tool - XilinxISE12.3, Spartan 3E, Speed Grade-4. Finally the results are compared with array and booth multiplier architectures. Proposed multiplier is better in terms of delay and area as compared to booth multiplier and array multiplier respectively. The proposed multiplier architecture can be used for high-speed requirements.