International Journal of Image, Graphics and Signal Processing (IJIGSP)
IJIGSP Vol. 6, No. 6, 8 May 2014
Cover page and Table of Contents: PDF (size: 558KB)
Pipelined Vedic-Array Multiplier Architecture
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Author(s)
Vaijyanath Kunchigik
1,*
Linganagouda Kulkarni
2
Subhash Kulkarni
3
Index Terms
Vedic, Array, Multiplier, Booth, High Speed
Abstract
In this paper, pipelined Vedic-Array multiplier architecture is proposed. The most significant aspect of the proposed multiplier architecture method is that, the developed multiplier architecture is designed based on the Vedic and Array methods of multiplier architecture. The multiplier architecture is optimized in terms of multiplication and addition to achieve efficiency in terms of area, delay and power. This also gives chances for modular design where smaller block can be used to design the bigger one. So the design complexity gets reduced for inputs of larger number of bits and modularity gets increased. The proposed Vedic-Array multiplier is coded in Verilog, synthesized and simulated using EDA (Electronic Design Automation) tool - XilinxISE12.3, Spartan 3E, Speed Grade-4. Finally the results are compared with array and booth multiplier architectures. Proposed multiplier is better in terms of delay and area as compared to booth multiplier and array multiplier respectively. The proposed multiplier architecture can be used for high-speed requirements.
Cite This Paper
Vaijyanath Kunchigik, Linganagouda Kulkarni, Subhash Kulkarni,"Pipelined Vedic-Array Multiplier Architecture", IJIGSP, vol.6, no.6, pp. 58-64, 2014. DOI: 10.5815/ijigsp.2014.06.08
Reference
[1]Zhijun Huang, Milo? D. Ercegovac, "High-Performance Left-to-Right Array Multiplier Design," arith, pp.4, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003.
[2]Ramalatha, M Dayalan, K D Dharani, P Priya, and S Deborah, "High speed energy efficient ALU design using Vedic multiplication techniques", ICACTEA, 2009. pp. 600-3, Jul 15-17, 2009.
[3]Shripad Kulkarni, "Discrete Fourier Transform (DFT) by using Vedic Mathematics"Papers on implementation of DSP algorithms/VLSI structures using Vedic Mathematics, 2006, www.edaindia.com, IC Design portal.
[4]M.B. Damle, Dr. S. S. Limaye, " Low-power Full Adder array-based Multiplier with Domino Logic," IOSR Journal of Electronics and Communication Engineering (IOSRJECE), ISSN : 2278-2834 Volume 1, Issue 1 (May-June 2012), PP 18-22.
[5]Sumit R. Vaidya, D. R. Dandekar, "Performance Comparison of Multipliers for Power-Speed Trade-off in VLSI Design," RECENT ADVANCES in NETWORKING, VLSI and SIGNAL PROCESSING, ISSN: 1790-5117, ISBN: 978-960-474-162-5.
[6]Pushpalata Verma, K. K. Mehta, " Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool," International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249 –8958, Volume-1, Issue-5, June 2012.
[7]Manoranjan Pradhan, Rutuparna Panda, Sushanta Kumar Sahu, "Speed Comparison of 16x16 Vedic Multipliers," International Journal of Computer Applications (0975 – 8887),Volume 21– No.6, May 2011.
[8]G.Ganesh Kumar, V.Charishma, " Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques", International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012 1 ISSN 2250-3153.
[9]Sumit Vaidya, Deepak Dandekar, "DELAY-POWER PERFORMANCE COMPARISON OF MULTIPLIERS IN VLSI CIRCUIT DESIGN", International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010.
[10]Sree Nivas A, Kayalvizhi N, " Implementation of Power Efficient Vedic Multiplier", International Journal of Computer Applications (0975 – 8887) Volume 43– No.16, April 2012.
[11]Soma BhanuTej, "Vedic Algorithms to develop green chips for future", Volume 2, Issue ICAEM12, February 2012, ISSN Online: 2277-2677 ,ICAEM12,Jan20,2012,Hyderabad,India.
[12]Krishnaveni D., Umarani T.G., " VLSI IMPLEMENTATION OF VEDIC MULTIP-LIER WITH REDUCED DELAY", International Journal of Advanced Technology & Engineering Research (IJATER) National Conference on Emerging Trends in Technology (NCET-Tech), ISSN No: 2250-3536 Volume 2, Issue 4, July 2012.
[13]Ramachandran.S, Kirti.S.Pande, " Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture", International Journal Of Computational Engineering Research / ISSN: 2250–3005.