International Journal of Image, Graphics and Signal Processing(IJIGSP)
ISSN: 2074-9074 (Print), ISSN: 2074-9082 (Online)
Published By: MECS Press
IJIGSP Vol.14, No.1, Feb. 2022
Optimized Low Power Dual Edge Triggered Flip-flop with Speed Enhancement
Full Text (PDF, 1547KB), PP.50-63
This paper gives a novel low-power approach with pulse generating circuits using dual edge triggered flip-flops. By doing so, flip-flop might operate at 1.2Volts, with the novel quick latch and conditional precharging. This paper aims at a new proposed low power dual edge triggered flip-flop with speed enhancement to achieve low power consumption with a shorter delay in power usage, hence, it is well suited for low-power digital system applications. The new proposed low power dual edge triggered flip-flop also aims at comparison with the three DETFF, Static Output Controlled Discharge Flip-Flop (SCDFF), Dual Edge Triggered Static Pulsed Flip-flop (DETSPFF), and Pervious work on Dual Edge Triggered flip-flop, proves to achieves with reduction in numbers of transistors in the stack and increases the number of charge-paths results in a faster operational speed. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16 % and 27.36 % less than that of previous arts DSPFF and SCDFF respectively. Clock-gated sense-amplifier is incorporated to reduce power consumption at low switching activity. The simulation is done using Cadence tool with 45nm standard CMOS technology.
Cite This Paper
Shilpa K.C, Lakshminarayana C, " Optimized Low Power Dual Edge Triggered Flip-flop with Speed Enhancement", International Journal of Image, Graphics and Signal Processing(IJIGSP), Vol.14, No.1, pp. 50-63, 2022.DOI: 10.5815/ijigsp.2022.01.05
Fa Lin,“Low-power pulse-Triggered Flip-Flop Design Based on a Signal Feed Through”,IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 22, No. 1, January 2014.
Yin-Tsung Hwang, Jin-Fa Lin and Ming-Hwa Sheu, “Low power pulse triggered flip flop design with conditional pulse enhancement scheme. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 361–366, Feb. 2012.
Alioto, E. Consoli, and G. Palumbo,“Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part II -results and figures of merit”,IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 5, pp. 737–750 , May 2011
Ke-Horng Chen, “Power Management Techniques for Integrated Circuit Design”, John Wiley & Sons Singapore Pte.Ltd., First Edition, ISBN:9781118896815.
Nedovic et al , “Novel dual edge triggered flip-flop”, International symposium on low power electronics and design.
Nitin Kumar Saini, “Low Power Dual Edge Triggered Flip-Flop”, International Conference on Signal Propagation and Computer Technology (ICSPCT),July2014
Wai Chung, Timothy Lo, and Manoj Sachdev, “A Comparative Analysis of Low-Power Low-Voltage Dual-Edge-Triggered Flip- Flops”,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, pp. 913-918,2002.
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija, “Conditional Precharge Techniques for Power-Efficient Dual-Edge Clocking”, International Symp. Low Power Electronics Design (ISPLED 2002), pp. 56-59, 2002
M. Pedram, Q. Wu, and X. Wu.(1998).A New Design of Double Edge Triggered FlipFlops.Proceedings of the Asian and South Pacific Design Automation Conference (ASPDAC'98), pp. 417-421, 1998.
Y. T. Liu, L. Y. Chiou, and S. J. Chang, “ Energy-Efficient Adaptive Clocking Dual Edge Sense Amplifier Flip-Flop”, IEEE International Symposium Circuits Systems (ISCAS), pp. 4329–4332, 2006.
Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat-Seng Yeo, “ Power Efficient Explicit Pulsed Dual Edge Triggered Sense Amplifi-er Flip-Flops”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 1, pp. 1-9, 2011.
Pawan Whig, Syed Naseem Ahmad,"Performance Analysis of Various Readout Circuits for Monitoring Quality of Water Using Analog Integrated Circuits", International Journal of Intelligent Systems and Applications(IJISA), vol.4, no.11, pp.91-98, 2012. DOI: 10.5815/ijisa.2012.11.11.
Souleymane KOUSSOUBE, Roger NOUSSI, Balira O. KONFE,"Using Description Logics to specify a Document Synthesis System", International Journal of Intelligent Systems and Applications(IJISA), vol.5, no.3, pp.13-22, 2013.DOI: 10.5815/ijisa.2013.03.02
Mohd Asyraf Mansor, Mohd Shareduwan M. Kasihmuddin, Saratha Sathasivam,"VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network", International Journal of Intelligent Systems and Applications(IJISA), Vol.8, No.9, pp.22-29, 2016. DOI: 10.5815/ijisa.2016.09.03.
Manisha B S, Rudraswamy S B,"VLSI Implementation of CMOS Full Adders with Low Leakage Power", International Journal of Computer Network and Information Security(IJCNIS), Vol.10, No.4, pp.20-27, 2018.DOI: 10.5815/ijcnis.2018.04.03.