International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 4, No. 7, 8 Jul. 2012
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FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller
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Author(s)
Vinod Kapse
1,*
Bhavana Jharia
1
S. S. Thakur
2
Index Terms
VLSI, FPGA, Pipelined, Inference Processor, Matching Degree
Abstract
This paper presents a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions. Analysis shows that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A FPGA based pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea, implemented on CycloneII-EP2C70F896C8. The controller is capable of processing fuzzified input.
The proposed controller is designed for 2-input 1-output with maximum clock rate is 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules, respectively.
Cite This Paper
Vinod Kapse, Bhavana Jharia, S. S. Thakur, "FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller", IJMECS, vol.4, no.7, pp.24-30, 2012. DOI:10.5815/ijmecs.2012.07.04
Reference
[1]K. Nakamura, N. Sakashita, Y. Nitta, K. Shimomura, and T. Tokuda, “Fuzzy inference and fuzzy inferenceprocessor,” IEEE Micro, Vol. 13, 1993, pp. 37-48.
[2]M. Togai and H. Watanabe, “Expert system on a chip: an engine for real-time approximate reasoning ,” IEEE Expert Magazine, Vol. 1, 1986, pp. 55-62.
[3]S.H.Huang et al, “High Speed Fuzzy Inference processor Using Active Rules Identification” JCIS 06-Joint conference on Information Sciences, Oct 8-11, 2006, Taiwan.R. J. Dirkman and J. Leonard,68HC11 Microcontroller Laboratory Workbook, Prentice Hall, 1996.
[4]J.Y. Lai et al, “A High Speed VLSI Fuzzy Logic Controller with Pipeline Architecture”, Proceedings of IEEE International Conference on Fuzzy Systems, vol. 3, pp.1054-1057, 2001
[5]F. Homburg and R. Palomera-Garcia, “A high-speed scalable and reconfigurable fuzzy controller,” in proceedings of IEEE International Symposium on Circuits and Systems, Vol. 5, 2003, pp. 797-800
[6]H. Peyravi, A. Khoei, and K. Hadidi, “Design of an analog CMOS fuzzy logic controller chip”, Fuzzy Sets and Systems 132, PP. 254-260, 2002.
[7]J. M. Jou and P. Y. Chen, “An adaptive fuzzy logic controller: its VLSI architecture and applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, 2000, pp. 52-60.
[8]R. D’Amore, O. Saotome, and K. H. Kienitz, “A two-input, one-output bit-scalable architecture for fuzzy processors,” IEEE Design and Test of Computers, 2001, pp.56-64.
[9]N. E. Evmorfopoulos, and J. N. Avaritsiots, “An adaptive digital fuzzy architecture for application- specific integrated circuits”, Active and Passive Elec. Comp., Vol. 25, pp. 289-306, 2002.
[10]E. Frias-Martinez, “Real-time fuzzy processor on a DSP,” in Proceedings of IEEE International Conference on Emerging Technologies and Factory Automation, Vol.1, 2001, pp. 403-408.
[11]Sajad A. Loan and Asim M. Murshid, “A Novel Fuzzy Inference Processor using Trapezoidal-Shaped Membership Function” Proceedings of the IEEE International Conference on Open Systems (ICOS2011), September 25 - 28, 2011, Langkawi, Malaysia.
[12]G. Asica, V. Catania, M. Russo, and L. Vita, “Rule driven VLSI fuzzy processor,” IEEE Micro, Vol. 1996, pp. 62-74.
[13]V. Salapura, “A fuzzy RISC processor” , IEEE Transactions on Fuzzy Systems, Vol.8, 2000, pp. 781-790.
[14]Shabiul Islam, Mukter Zaman, Bakri Madon, and Masuri Othman (2008). Designing Fuzzy Based Mobile Robot Controller using VHDL. International Journal of Mathematical Models and Methods in Applied Science, Issue 1, Volume 2, ,p-p 138-142.