Prateek Agrawal; S.R.P.Sinha; Neeraj Kumar Misra; Subodh Wairya

Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency

Full Text (PDF, 920KB), PP.11-20

Views: 0 Downloads: 0

Author(s)

Prateek Agrawal ^1,* S.R.P.Sinha ¹ Neeraj Kumar Misra ¹ Subodh Wairya ¹

1. Department of Electronics Engineering, Lucknow, India Institute of Engineering and Technology

* Corresponding author.

DOI: https://doi.org/10.5815/ijmecs.2016.08.02

Received: 22 Apr. 2016 / Revised: 12 May 2016 / Accepted: 23 Jun. 2016 / Published: 8 Aug. 2016

Index Terms

Quantum-dot cellular automata, Error control, Nano-communication, Parity generator, Parity checker, low power

Abstract

Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.

Cite This Paper

Prateek Agrawal, S.R.P.Sinha, Neeraj Kumar Misra, Subodh Wairya, "Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency", International Journal of Modern Education and Computer Science(IJMECS), Vol.8, No.8, pp.11-20, 2016. DOI:10.5815/ijmecs.2016.08.02

Reference

[1]C.S. Lent, S., P. Douglas Tougaw, Wolfgang Porod, and Gary H. Bernstein. "Quantum cellular automata." Nanotechnology 4, no. 1 (1993): 49.
[2]Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, "Frame of Reversible BCD Adder and Carry Skip BCD Adder and Optimization Using New Reversible Logic Gates for Quantum-Dot Cellular Automata", Australian Journal of Basic and Applied Sciences, vol 9, issue 31, pp. 286-298, 2015.
[3]Walus, Konrad, Timothy J. Dysart, Graham A. Jullien, and R. AriefBudiman. "QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata." Nanotechnology, IEEE Transactions on 3, no. 1 (2004): 26-31.
[4]Bibhash Sen, Manojit Dutta, Samik Some, and Biplab K. Sikdar. "Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU." ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 11, no. 3, page 30, 2014
[5]International Technology Roadmap for Semiconductors (ITRS), [Online]. Available: http://www.itrs.net
[6]Snider, Gregory L., Alexei O. Orlov, I. Amlani, X. Zuo, G. H. Bernstein, C. S. Lent, J. L. Merz, and W. Porod. "Quantum-dot cellular automata." Journal of Vacuum Science & Technology A 17, no. 4, pp.1394-1398, 1999.
[7]Prateek Agrawal, S.R.P. Sinha, and S. Wairya. "Quantum Dot Cellular Automata Based Parity Generator and Detector: A Review." International Journal of Electronics and Communication Engineering, no. 5, 3,(2016), 41-50.
[8]Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, "Approach to Design a High Performance fault-Tolerant Reversible ALU", International Journal of Circuit and Architectural design, Inderscience, vol. 2, no. 1, pp. 83-103, 2016.
[9]Seminario, Jorge M., Pedro A. Derosa, Luis E. Cordova, and Brian H. Bozard. "A molecular device operating at terahertz frequencies: theoretical simulations." IEEE Transactions on Nanotechnology, vol. 3, no. 1,pp. 215-218, 2004
[10]Neeraj Kumar Misra, Subodh Wairya, Vinod Kumar Singh, "Optimized Approach for Reversible Code Converters Using Quantum-Dot Cellular Automata", In Proceedings of the 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications (FICTA), Springer India, pp.367-378, 2016.
[11]Lent, Craig S., and Beth Isaksen. "Clocked molecular quantum-dot cellular automata." IEEE Transactions on Electron Devices, 50, no. 9, pp. 1890-1896, 2003.
[12]Orlov, A. O., G. Toth, I. Amlani, R. Kummamuru, R. Ramasubramaniam, C. S. Lent, G. H. Bernstein, and G. L. Snider. "Experimental studies of clocked quantum-dot cellular automata devices." In Device Research Conference, 2000. Conference Digest. 58th DRC, pp. 157-158, 2000.
[13]Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, "Approaches to Design Feasible Error Control Scheme Based on Reversible Series Gates" European Journal of Scientific Research, vol. 129, no. 3, pp. 224-240, 2015.
[14]Qadir, Fasel, Peer Zahoor Ahmad, Shahi Jahan Wani, and M. A. Peer. "Quantum-Dot Cellular Automata: Theory and Application." In Machine Intelligence and Research Advancement (ICMIRA), 2013 International Conference on, pp. 540-544. IEEE, 2013.
[15]Gurmohan Singh, R. K. Sarin, and Balwinder Raj. "A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis." Journal of Computational Electronics 15.2, pp. 455-465, 2016
[16]Chakraborty, Rupak, Debashis De, Ajmal Khan, Chhandak Mukherjee, and Sarah Pramanik. "Effect of temperature and kink energy in multilevel digital circuit using Quantum dot cellular automata." In Computers and Devices for Communication (CODEC), 2012 5th International Conference on, pp. 1-4. IEEE, 2012.
[17]Saket Srivastava, Arjun Asthana, SanjuktaBhanja, and Sudeep Sarkar. "QCAPro-an error-power estimation tool for QCA circuit design." In Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, pp. 2377-2380. IEEE, 2011.
[18]Bibhash Sen, Siddhant Ganeriwal, and Biplab K. Sikdar. "Reversible logic-based fault-tolerant nanocircuits in QCA." ISRN Electronics, 2013.
[19]Saket Srivastava, Sudeep Sarkar, and SanjuktaBhanja. "Estimation of upper bound of power dissipation in QCA circuits." IEEE Transactions on Nanotechnology, vol. 8, no. 1 pp. 116-127, 2008.
[20]S. Shin, G. Lee, and K. Yoo, "Design of Exclusive-OR Logic Gate on Quantum-Dot Cellular Automata," International Journal of Control and Automation, 8, 95-104, 2015.
[21]M. Mustafa, and M. R. Beigh, "Design and implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count," Indian Journal of Pure and Applied Physics, 51, pp. 60-66, 2013.
[22]Firdous Ahmad, Peer Zahoor Ahmad, and G. Mohiud din Bhat. "Design and analysis of odd-and even-parity generators and checkers using Quantum-dot Cellular Automata (QCA)." In Computing for Sustainable Global Development (INDIACom), 2015 2nd International Conference on, pp. 187-194, 2015.
[23]Santanu Santra, and Utpal Roy. "Design and Optimization of Parity Generator and Parity Checker Based On Quantum-dot Cellular Automata."World Academy of Science, Engineering and Technology, International Journal of Computer, Electrical, Automation, Control and Information Engineering 8, no. 3, pp. 491-497, 2014.
[24]N. R. G, P. C. Srikanth, and P. Sharan, "A novel quantum-dot cellular automata for parity bit generator and parity checker,"International Journal of Emerging Technology in Computer Science & Electronics, 14, 2015.

International Journal of Modern Education and Computer Science (IJMECS)