Neeta Pandey; Saurabh Gupta

Design and Implementation of Novel Multiplier using Barrel Shifters

Full Text (PDF, 495KB), PP.28-34

Views: 0 Downloads: 0

Author(s)

Neeta Pandey ^1,* Saurabh Gupta ¹

1. Dept. of Electronics and Communication Engg, Delhi Technological University, Bawana Road, Delhi, 110042, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijigsp.2015.08.03

Received: 27 Mar. 2015 / Revised: 5 May 2015 / Accepted: 9 Jun. 2015 / Published: 8 Jul. 2015

Index Terms

Barrel shifter, modified Booths algorithm, multiplier design

Abstract

The paper presents a design scheme to provide a faster implementation of multiplication of two signed or unsigned numbers. The proposed scheme uses modified booth's algorithm in conjunction with barrel shifters. It provides a uniform architecture which makes upgrading to a bigger multiplier much easier than other schemes. The verification of the proposed scheme is illustrated through implementation of 16x16 multiplier using ISIM simulator of Xilinx Design Suite ISE 14.2. The scheme is also mapped onto hardware using Xilinx Zynq 702 System on Chip. The performance is compared with existing schemes and it is found that the proposed scheme outperform in terms of delay.

Cite This Paper

Neeta Pandey, Saurabh Gupta"Design and Implementation of Novel Multiplier using Barrel Shifters", IJIGSP, vol.7, no.8, pp.28-34, 2015. DOI: 10.5815/ijigsp.2015.08.03

Reference

[1]J. H. Cline, "Barrel shifter using bit reversers and having automatic normalization", US 4782457 A, 1988.

[2]M. J. S. Smith, Application Specific Integrated circuits, Pearson, 2006.

[3]M. Ercegovac, and T. Lang, Digital Arithmetic, San Francisco, Morgan Kaufmann, 2004.

[4]B. Pahrami, Computer Aithmatic and Hardware Design, New York, Oxford University Press, 2000.

[5]N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuit and System perspective, Pearson, 2006.

[6]M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits A Design Perspective, PHI, 2003.

[7]K. S. Yeo, and K. Roy, Low Voltage Low Power VLSI Subsystems, Tata Mc-Graw Hill, 2009.

[8]V. Kunchigik, L. Kulkarni, and S. Kulkarni, "Pipelined Vedic-Array Multiplier Architecture", International Journal of Image, Graphics and Signal Processing (IJIGSP)", vol. 6, No. 6, pp. 58-64, 2014

[9]P. M. Kogge, and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations", IEEE Transactions on Computers, vol. C-22, pp. 786–793, 1973.

[10]J. Sklansky, "Conditional-sum addition logic", IRE Transactions on Electronic Computers, vol. 9, pp. 226–231, 1960.

[11]R. P. Brent, and H. T. Kung, "A Regular Layout for Parallel Adders", IEEE Transactions on Computers, vol. C-31, (1982), 260–264,.

[12]T. Han, and D. Carlson, "Fast area-efficient VLSI adders", in Proceedings of IEEE Symposium on Computer Arithmetic, pp. 49–56, 1987.

[13]H. Ling, "High-speed binary adder", IBM Journal of Research and Development, vol. 25, pp. 156–166, 1981.

International Journal of Image, Graphics and Signal Processing (IJIGSP)